Fox G20 GPIO NOTES =-=-=-=-=-=-=-=-=- Fox G20 GPIO lines ================== The AT91SAM9G20 has 96 GPIO lines arranged in 3 banks of 32: PA0 to PA31, PB0 to PB31 and PC0 to PC31. Each bank has a separate PIO controller: PIOA, PIOB and PIOC. All GPIO lines on PIOA and PIOB run at the same power supply voltage which the G20 configures as 3.3 volts. PC0 to PC3 run at the analog voltage AVDD (J6.33) and the corresponding analog ground is AGND (J6.35). PC4-PC31 all run at the same power supply voltage which the G20 configures as 1.8 volts. No GPIO lines can tolerate voltages above +4 volts or below -0.3 volts. More precisely PA0 to PA31 and PB0 to PB31 should not have input voltages above 3.6 volts (3.3 volt supply plus 0.3 volts). PC0 to PC3 input voltages should not exceed 3.6 volts (assuming AVDD is 3.3 volts). PC4 to PC31 input voltages should not exceed 2.1 volts. Given those voltage settings the current passing through PA0 to PA31, PB0 to PB31 and PC0 to PC3 should not exceed 8 milliamps. The current passing through PC4 to PC31 ++ should not exceed 4 milliamps. Each GPIO line can either be a fully user configurable general purpose IO or it can be associated with "Peripheral A" or "Peripheral B". The AT91SAM9G20 manual has three tables showing the mapping of "Peripheral A" and "Peripheral B" to the 32 lines on each PIO. It is in a section titled: "Peripheral Signal Multiplexing on I/O Lines" (and is section 10.3 in the preliminary manual dated 05-February-10). An interesting feature of the multiplexing on I/O lines is that it only applies to the output direction. In the input direction the external line can be thought of as connecting to the gpio (PIO) function and the peripheral A and B functions at the same time. See the "I/O Line Control Logic" (Figure 29-3 in the preliminary manual) for more information. An example of an output (or bidirectional) line: PA23 can either be: a) TWD [Peripheral A] on-chip "two wire" interface (I2C) data line b) ETX2 [Peripheral B] optional data line for ethernet c) a user configurable GPIO line (i.e. PIO controller) Of the distributions I am aware of, PA23 is either configured as a) or c). When the Debian distribution configures that line as c) it then allocates it to the kernel's i2c-gpio driver which does I2C bit-banging. In a sense the Debian distribution has stolen PA23 from the pool of user configurable GPIO lines. The kernel code in this area suggests that the Atmel on-chip TWI logic is suspect and it is better to use the kernel's own (bit banging) driver ***. Note that PA23 maps to the FoxG20 J6.32 pin which was called I2C_DATA on the FoxLX. And J6.31 is the corresponding I2C clock on both the LX and the G20. Luckily not all GPIO lines have as complicated a history as PA23. The internal pullup on PA0 to PA31, PB0 to PB31 and PC0 to PC3 is minimum 40 Kohms, typical 75 kohms and maximum 190 kohms. The internal pullup on PC4 to PC31 is minimum 240 Kohms and maximum 1 Mohm. In the absence of any other settings by the AT91Bootstrap, Acmeboot/uBoot, the Linux kernel and user space programs GPIO lines are initialized to input with the pullup resistor making them appear at the higher voltage for that line. PA* PB* PC* ------------------------------------------------------------------- PA0 spi0,sd_b PB0 J7.9 [spi1] PC0 J6.30 AD0 PA1 spi0,sd_b PB1 J7.10 [spi1] PC1 J6.29 AD1 PA2 spi0 PB2 J7.7 [spi1] PC2 J6.28 AD2 PA3 spi0_cs0,sd_b PB3 J7.8 [spi1_cs0] PC3 J6.27 AD3 PA4 sd_b PB4 J6.9 TXD0 PC4 SW1 ^^^ PA5 sd_b PB5 J6.8 RXD0 PC5 J7.19 [spi1_cs1] PA6 sd_a,J6.24 PB6 J6.5 TXD1 PC6 J7.20 ## usb_dev+5 PA7 sd_a,J6.25 PB7 J6.4 RXD1 PC7 J7.17 red_led PA8 sd_* [J6.23] PB8 J7.22 TXD2** PC8 J7.18 RTS3 PA9 sd_a,J6.26 PB9 J7.21 RXD2** PC9 J7.15 PA10 sd_a,J6.36 PB10 J6.14 TXD3 PC10 J7.16 CTS3 PA11 sd_a,J6.38 PB11 J6.13 RXD3 PC11 spi0_cs1(df) PA12 eth PB12 J6.16 TXD5 PC12 J7.13 PA13 eth PB13 J6.15 RXD5 PC13 J7.14 PA14 eth PB14 J10.4 dRXD PC14 J7.11 PA15 eth PB15 J10.3 dTXD PC15 J7.12 PA16 eth PB16 J7.5 [W1] PC16 d16 ++ PA17 eth PB17 J7.6 PC17 d17 PA18 eth PB18 J7.3 PC18 d18 PA19 eth PB19 J7.4 PC19 d19 PA20 eth PB20 J6.18 PC20 d20 PA21 eth PB21 J6.17 PC21 d21 PA22 J6.37 PB22 J7.32 DSR0 PC22 d22 PA23 J6.32 SDA PB23 J7.31 DCD0 PC23 d23 PA24 J6.31 SCL PB24 J7.34 DTR0 PC24 d24 PA25 J7.38 PB25 J7.33 RI0 PC25 d25 PA26 J7.37 PB26 J6.7 RTS0 PC26 d26 PA27 J7.36 PB27 J6.10 CTS0 PC27 d27 PA28 J7.35 PB28 J6.3 RTS1 PC28 d28 PA29 eth [W1 V2] PB29 J6.6 CTS1 PC29 d29 PA30 J6.22 RXD4 PB30 J6.20 PC30 d30 PA31 J6.21 TXD4 PB31 J6.19 PC31 d31 Each entry starts with the AT91SAM9G20 GPIO line name followed optionally by a FoxG20 pin name (starting with the letter "J") followed optionally by a function (other than normal GPIO action) that may be associated with this line. These start with lower cases letters representing some on-chip (i.e. AT91SAM9G20) function: - eth: for ethernet (Atmel: EMAC) - sd_b: microSD card (Atmel: MCI slot B) in FoxG20 V1+V2 - sd_a: microSD card (Atmel: MCI slot A) in FoxG20 V2 - spi0: SPI to dataflash (Atmel: SPI slave 0) - d16 to d31: upper 16 bits of databus to RAM sd_b on the FoxG20 V1 used the MMC interface (i.e. MCI silicon within the AT91SAM9G20). In the FoxG20 V2 design sd_a is added and looks like being the primary SD card and uses the MMC interface. Also in the FoxG20 V2 design sd_b is set up to use either the MMC or the SPI interface with board links set for SPI (since the clock comes from PA2). PB16 J7.5 may be used for the "One Wire" protocol which is known inside the Linux kernel as "w1". The FoxG20 V2 circuit shows PA29 going to a one wire device: DS28EA00 . FoxG20 J6, J7, J10, J16 Pinouts =============================== These four connectors have 0.1" spacing (2.54 mm). J6 and J7 are both 40 pin arranged as 2 rows of 20 pins. J10 is a 6 pin connector and J16 is a 5 pin connector. "Not connected to" means that a pin goes to a point on the FoxG20 main (larger) board, typically to a spot marked for a resistor and there is no resistor (or link) connected. For example J6.11 goes to R8 which is marked on the schematic as "0 N.M." and no resistor or link is present. [Both R8 and R10 are hard to find being on the top of the main PCB in the vicinity of J2 and J6 (partially hidden by the NetusG20 module).] Unless otherwise noted, pins that only have a GPIO line in the description (e.g. J7.3 PB18) are available for GPIO use at 3.3 volt logic levels. J6 Description [20x2] | J7 Description [20x2] ----------------------------------|---------------------------------- J6.1 3v3 DC power | J7.1 GND [ground DC power] J6.2 3v3 DC power | J7.2 GND [ground DC power] J6.3 PB28 RTS1 [ttyS2] | J7.3 PB18 J6.4 PB7 RXD1 [ttyS2] | J7.4 PB19 J6.5 PB6 TXD1 [ttyS2] | J7.5 PB16 J6.6 PB29 CTS1 [ttyS2] | J7.6 PB17 J6.7 PB26 RTS0 [ttyS1] | J7.7 PB2 J6.8 PB5 RXD0 [ttyS1] | J7.8 PB3 J6.9 PB4 TXD0 [ttyS1] | J7.9 PB0 J6.10 PB27 CTS0 [ttyS1] | J7.10 PB1 J6.11 Not connected to 3v3 aux | J7.11 PC14 1v8 J6.12 5 volt DC power | J7.12 PC15 1v8 J6.13 PB11 RXD3 [ttyS4] | J7.13 PC12 1v8 J6.14 PB10 TXD3 [ttyS4] | J7.14 PC13 1v8 J6.15 PB13 RXD5 [ttyS6] | J7.15 PC9 1v8 J6.16 PB12 TXD5 [ttyS6] | J7.16 PC10 CTS3 [ttyS4] 1v8 J6.17 PB21 | J7.17 PC7 Red LED [out] 1v8 J6.18 PB20 | J7.18 PC8 RTS3 [ttyS4] 1v8 J6.19 PB31 | J7.19 PC5 1v8 J6.20 PB30 | J7.20 PC6 reserved, detect USB device J6.21 PA31 RXD4 [ttyS5] | J7.21 PB9 RXD2 [ttyS3] J6.22 PA30 TXD4 [ttyS5] | J7.22 PB8 TXD2 [ttyS3] J6.23 Not connected to PA8 | J7.23 Battery [in to netusg20] +++ J6.24 PA6 sd_a | J7.24 Power good [from NetusPS1] J6.25 PA7 sd_a | J7.25 POK [PS1 3v3 aux stable] J6.26 PA9 sd_a | J7.26 SHDNPS# [PS1 shutdown when low] J6.27 PC3 AD3 [analog in] | J7.27 NRST [G20 MPU reset when low] J6.28 PC2 AD2 [analog in] | J7.28 SHDN# [out from G20 MPU ??] J6.29 PC1 AD1 [analog in] | J7.29 5 volt DC power J6.30 PC0 AD0 [analog in] | J7.30 WAKEUP [in to G20 MPU] J6.31 PA24 SCL [I2C clock] | J7.31 PB23 DCD0 [ttyS1] J6.32 PA23 SDA [I2C data] | J7.32 PB22 DSR0 [ttyS1] J6.33 AVDD [3v3 aux, out] | J7.33 PB25 RI0 [ttyS1] J6.34 VREF [analog ref, in] | J7.34 PB24 DTR0 [ttyS1] J6.35 AGND [analog ground] | J7.35 PA28 J6.36 PA10 sd_a | J7.36 PA27 J6.37 PA22 | J7.37 PA26 J6.38 PA11 sd_a | J7.38 PA25 J6.39 GND [ground DC power] | J7.39 3v3 DC power J6.40 GND [ground DC power] | J7.40 3v3 DC power J10 Description [Debug connector] -------------------------------------- J10.1 3v3 DC power J10.2 PA24 SCL [I2C clock] ^^ J10.3 PB15 DTXD [ttyS0+bootup] J10.4 PB14 DRXD [ttyS0+bootup] J10.5 PA23 SDA [I2C data] ^^ J10.6 GND [ground DC power] J16 ### Description [oLED display] ----------------------------------- J16.1 5 volt DC power [optionally switched by PC14] J16.2 PB9 RXD2 [ttyS3] J16.3 PB8 TXD2 [ttyS3] J16.4 GND [ground DC power] J16.5 Not connected Notes ===== ++ PC16 to PC31 on the FoxG20 are used for the upper 16 bits of the data bus to the 64 MB of RAM on the NetusG20 module. So they are not available for other GPIO use. +++ J7.23 is a diode (voltage) drop from the CR1220 battery on the FoxG20 card. It is also a diode drop from 3v3aux power supply line. So a design may remove the CR1220 battery on the FoxG20 card and supply its own 3 volt battery whose positive side is connected to J7.23 . In either case the battery will only supply current when the 3v3aux line is off (i.e. not supplying power). ** PB8 also is J16.3 and PB9 is J16.2 *** my experiments indicate the TWI (I2C) silicon in the AT91SAM9G20 works fine and the derogatory comments in the Linux kernel are outdated (i.e. probably refer to an earlier Atmel device). ^^ Marked "N.M." (not mounted) on the schematic but my newer board has them connected (and my older board doesn't). ^^^ When CONFIG_KEYBOARD_GPIO is defined in the kernel build, PC4 is associated with the "gpio-keys" input device (and hence not available through the normal gpio interface). See foxg20_pc4.txt ## in V1 PC6 was a detector for usb_dev (mini USB connector) 5 volt. In V2 the main 5 volts to board comes in via the usb_dev connector so there is no point to wire it to PC6; instead PC6 goes through a transistor (Q1) whose collector becomes "pin6" on D1. ### J16 is not present in the FoxG20 Version 2 D. Gilbert 20111129